1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device having a floating spacer and a method of forming the same.
2. Description of the Prior Art
The critical dimension (CD) in semiconductor processes has become ever finer with the increasing miniaturization of semiconductor devices. Along with the continuously shrinking of this dimension, the integrated process of forming a semiconductor device having a metal gate also faces more challenges and limitations.
As the semiconductor industry progresses into nanometer technology process nodes in pursuit of highly integrated and high-speed operation, current techniques utilize miniaturized through holes and inter-layer dielectric layers to form a multilayered an interconnected wiring structure. The method of forming such interconnected wiring structure includes forming a through hole in a dielectric layer, and then sequentially forming various films in the through hole, such as an adhesive layer, a barrier layer and a conductive layer. When the CD of the semiconductor device goes below 14 nanometers (nm), the current techniques can no longer define the position of the through hole, as well as controlling the CD thereof. If a dimensional shift or a dislocated through hole occurs, this can easily lead to serious defects to other elements, thereby affecting the entire performance of the semiconductor device.
For these reasons, current semiconductor devices having metal gates still meet practical requirements, but the current approach for forming such semiconductor device also encounters numerous problems. Therefore, how to improve the current issues while increasing the performance of the device has become an important task in this field.